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CPC5610/CPC5611
LITELINKTM II Silicon Data Access Arrangement (DAA) IC
Features
* * * * * * * * * * * * Full-duplex data and voice transmission Transformerless telephone line isolation interface Operates at all modem speeds, including V.90 (56K) 3.3 or 5 V power supply operation Half-wave ring detector (CPC5610) or full-wave ring detector (CPC5611) Caller ID signal reception Small 32-pin SOIC plastic package Printed-circuit board space and cost savings Meets PC Card (PCMCIA) height requirements Easy interface with modem ICs and voice CODECs Worldwide dial-up telephone network compatibility Supplied application circuit complies with the requirements of TIA/EIA/IS-968 (FCC part 68), UL1950, UL60950, EN60950, IEC60950, EN55022B, CISPR22B, EN55024, and TBR-21 CPC5610 and CPC5611 comply with UL1577 TTL compatible logic inputs and outputs Line-side circuit powered from telephone line
Description
Clare CPC5610 and CPC5611 LITELINKs are silicon data access arrangement (DAA) ICs used in data and voice communication applications to make connections to the public switched telephone network (PSTN). LITELINK uses on-chip optical components and a few inexpensive external components to form a complete voice or high-speed data telephone line interface. LITELINK eliminates the need for the large isolation transformers or capacitors as used in other DAA configurations. It incorporates the required high-voltage isolation barrier in the surface-mount SOIC package. The CPC5610 (half-wave ring detect) and CPC5611 (full-wave ring detect) build upon Clare's existing LITELINK line, with improved performance and 3.3 V operation.
* * *
Ordering Information Applications
* * * * * * * * Satellite and cable set-top boxes V.90 (and other standard) modems Fax machines Voicemail systems Computer telephony PBXs Telephony gateways Embedded modems for such applications as POS terminals, automated banking, remote metering, vending machines, security, and surveillance Part Number CPC5610A CPC5610ATR CPC5611A CPC5611ATR Description 32-pin surface mount DAA with half-wave ring detect, tubed 32-pin surface mount DAA with half-wave ring detect, tape and reel 32-pin surface mount DAA with full-wave ring detect, tubed 32-pin surface mount DAA with full-wave ring detect, tape and reel
Figure 1. CPC5610/CPC5611 Block Diagram
TIP+ Isolation Barrier Transmit Isolation Amplifier Tx+ TxTransmit Diff. Amplifier Transconductance Stage 2-4 Wire Hybrid AC/DC Termination Hookswitch VI Slope Control AC Impedance Control Current Limit Control
OH RING CID Vref AGC
Vref AGC
RING-
Receive Isolation Amplifier Rx+ RxReceive Diff. Amplifier CID/ RING MUX CSNOOP Snoop Amplifier CSNOOP RSNOOP RSNOOP
DS-CPC5610/5611-R9.0
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1
CPC5610/CPC5611
1 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Resistive Termination Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Resistive Termination Application Circuit Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Reactive Termination Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Reactive Termination Application Circuit Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Using LITELINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Switch Hook Control (On-hook and Off-hook States) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 On-hook Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Ring Signal Detection via the Snoop Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Polarity Reversal Detection with CPC5611 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 On-hook Caller ID Signal Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Off-Hook Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Receive Signal Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Transmit Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Resistive Termination Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Reactive Termination Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Resistive Termination Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Reactive Termination Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 5 6 6 7 8 9
10 10 10 10 11 11 11 11 12 12 12 12 13 13 13
4 Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 LITELINK Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Clare, Inc. Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 Third Party Design Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 LITELINK Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 Manufacturing Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 18 18 18 18 18
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R9.0
CPC5610/CPC5611
1. Electrical Specifications
1.1 Absolute Maximum Ratings
Parameter Isolation Voltage Continuous Tip to Ring Current (RZDC = 5.2) Total Package Power Dissipation Operating temperature Storage temperature Soldering temperature 0 -40 Minimum Maximum 1500 150 1 +85 +125 +220 Unit VRMS mA W C C C
Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and affect its reliability.
1.2 Performance
Parameter DC Characteristics Operating Voltage VDD Operating Current IDD Operating Voltage VDDL Operating Current IDDL On-hook Characteristics Metallic DC Resistance Longitudinal DC Resistance Ring Signal Detect Level Ring Signal Detect Level Snoop Circuit Frequency Response Snoop Circuit CMRR Ringer Equivalence Longitudinal Balance Off-Hook Characteristics AC Impedance Longitudinal Balance Return Loss Transmit and Receive Characteristics Frequency Response Trans-Hybrid Loss Transmit and Receive Insertion Loss Average In-band Noise Harmonic Distortion
Rev. 9.0
Minimum 3.0 2.8 10 10 5 28 166 60
Typical 10.5 -40 0.1B -
Maximum 5.50 10 3.2 12 >4000 -
Unit V mA V mA M M VRMS VRMS Hz dB REN dB dB dB Hz dB dB dBm/Hz dB
Conditions Host side Host side Line side, derived from tip and ring Line side, drawn from tip and ring while off-hook Tip to ring, 100 Vdc applied 150 Vdc applied from tip and ring to Earth ground 68 Hz ring signal applied to tip and ring 15 Hz ring signal applied across tip and ring -3 dB corner frequency @ 166 Hz 120 VRMS 60 Hz common mode signal across tip and ring Per FCC part 68.3 Tip to ring, using resistive termination application circuit Per FCC part 68.3 Into 600 at 1800 Hz -3 dB corner frequency 30 Hz Into 600 at 1800 Hz, with C18 30 Hz to 4 kHz 4 kHz flat bandwidth -3 dBm, 600 Hz, 2nd harmonic 3
40 30 -1 -
600 26 36 0 -120 -80
4000 1 www.clare.com
CPC5610/CPC5611
Parameter Transmit Level Receive Level RX+/RX- Output Drive Current TX+/TX- Input Impedance Isolation Characteristics Isolation Voltage Surge Rise Time OH and CID Control Logic Inputs Input Threshold Voltage High Level Input Current Low Level Input Current RING Output Logic Levels Output High Voltage Output Low Voltage VDD -0.4 0.4 V V IOUT = -400 A IOUT = 1 mA 0.8 -120 2.0 0 -120 V A A VINVDD VIN=GND 1500 2000 VRMS V/S Line side to host side No damage via tip and ring Minimum 60 Typical 0 90 Maximum 2.2 2.2 0.5 120 Unit VP-P VP-P mA k Conditions Single-tone sine wave. Or 0 dBm into 600 . Single-tone sine wave. Or 0 dBm into 600 . Sink and source
Specifications subject to change without notice. All performance characteristics based on the use of Clare, Inc. application circuits. Functional operation of the device at conditions beyond those specified here is not implied. Specification conditions: VDD = 5V, temperature = 25 C, unless otherwise indicated.
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Rev. 9.0
CPC5610/CPC5611 1.3 Pin Description
Pin 1 2 3 4 5 6 7 8 9 Name VDD TXSM TXTX+ TX REFM GND OH RING Function Host (CPE) side power supply Transmit summing junction Negative differential transmit signal to DAA from host Positive differential transmit signal to DAA from host Transmit differential amplifier output Internal voltage reference Host (CPE) side analog ground Assert logic low for off-hook operation Indicates ring signal, pulsed high to low Assert logic low while on hook to place CID information on RX pins. Negative differential analog signal received from the telephone line. Must be AC coupled with 0.1 F. Positive differential analog signal received from the telephone line. Must be AC coupled with 0.1 F. Positive differential snoop input Negative differential snoop input Receive photodiode amplifier output Receive photodiode summing junction Power supply for line side, regulated from tip and ring. Receive isolation amp summing junction Receive LED pre-bias current set Bridge rectifier return Electronic inductor and DC current limit DC feedback output V to I slope control 0.625 Vdc reference External MOSFET gate control Receive signal input Bridge rectifier return Transmit photodiode summing junction Receiver impedance set Transmit transconductance gain set Transmit photodiode amplifier output 1.25 Vdc reference Figure 2. Pinout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD TXSM TXTX+ TX REFM GND OH RING CID RXRX+ SNP+ SNPRXF RX REFL TXF ZTX ZNT TXSL BRNTS GAT REFB DCS1 DCS2 ZDC BRRPB RXS VDDL 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
10 CID 11 RX-
12 RX+ 13 SNP+ 14 SNP15 RXF 16 RX 17 VDDL 18 RXS 19 RPB 20 BR21 ZDC 22 DCS2 23 DCS1 24 REFB 25 GAT 26 NTS 27 BR28 TXSL 29 ZNT 30 ZTX 31 TXF 32 REFL
Rev. 9.0
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5
CPC5610/CPC5611
2. Application Circuits
LITELINK can be used with telephone networks worldwide. Some public telephone networks, notably in North America and Japan require resistive line temrination. Other telephone networks in Europe and elsewhere require reactive line termination. The application circuits below address both line termination models. The reactive termination application circuit (see Section 2.2 on page 8) describes a TBR-21 implementation. This circuit can be adapted easily for other reactive termination needs. Worldwide application of LITELINK is described more fully in Clare application note AN-147, Worldwide Application of LITELINK.
2.1 Resistive Termination Application Circuit
Figure 3. Resistive Termination Application Circuit Schematic
3.3 or 5 V R23 10 C16 10 FB1 600 200 mA A 1 R1 (RTX) 80.6K 1% TXTX+ C13 0.1 C2 0.1 C3 0.1 2 3 4 5 6 7 OH RING CID RXRX+ 8 9 VDD TXSM TXTX+ TX REFM GND OH RING C1 1 C9 0.1 A U1 LITELINK REFL TXF ZTX ZNT TXSL BR1NTS GAT REFB DCS1 DCS2 ZDC BR2RPB RXS VDDL 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 R4 (RPB) 68.1 1% -BR R8 (RHTX) 200K 1% R9 (RHNT) 200K 1% R10 (RZNT) 301 1% -BR C18 15 pF R18 (RZTX) 150 1% -BR SP1 P3100SB 1 TIP -BR R15 (RDCS2) 1.69M 1% R16 (RZDC) 8.2 1% R20 (RVDDL) 2 DB1 SIZB60 + 600V_60A R12 (RNTF) 1M 1% R14 (RGAT) 47 -BR C12 (CDCS) 0.027 R13 (RNTS) 1M 1% -BR R5 (RTXF) 42.2K 1% C10 0.01 500V C15 0.01 500V
Q1 CPC5602C
-BR
R22 (RDCS1A) 6.8 M 1% R21 (RDCS1B) 6.2 M 1%
10 CID C14 0.1 11 RXC4 0.1 12 RX+ 13 SNP+ 14 SNP15 RXF 16 RX R2 (RRXF) 127K 1%
-
A
-BR 2 RING
NOTE: Unless otherwise noted, all resistors are in Ohms, 5%. All capacitors are in microFarads.
C7 (CSNP-) 220pF 2000V R3 (RSNPD) 1.5M 1% R6 (RSNP-2) 1.8M 1/10W 1% R44 (RSNP-1) 1.8M 1/10W 1%
R7 (RSNP+2) C8 (CSNP+) 1.8M 1/10W 1% 220pF 2000V
R45 (RSNP+1) 1.8M 1/10W 1%
1 This design was tested and found to comply with FCC Part 68 with this part. Other compliance requirements may require a different part. 2 Higher-noise power supplies may require substitution of a 220 H inductor, Toko 380HB-2215 or similar. See the Power Quality section of Clare application note AN-146, Guidelines for Effective LITELINK Designs for more information. 3
Optional for enhanced trans-hybrid loss, see "Trans-Hybrid Loss" on page 16.
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Rev. 9.0
CPC5610/CPC5611
2.1.1 Resistive Termination Application Circuit Part List
Quantity 1 6 2 2 1 1 1 1 1 1 1 1 4 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1
1Through-hole
Reference Designator C1 C2, C3, C4, C9, C13, C14 C7, C81 C10, C151 C12 C16 C18 (optional) R1 R2 R3 R4 R5 R6, R7, R44, R451 R8, R9 R10 R12, R13 R14 R15 R16 R18 R20 R21 R22 R23 FB1 DB1 SP1 Q1 U1
Description 1 F, 16 V, 10% 0.1 F, 16 V, 10% 220 pF, 2 kV, 5% 0.01 F, 500 V, 10% 0.027 F, 16 V, 10% 10 F, 16 V, 10% 15 pF, 16V, 10% 80.6 k, 1/16 W, 1% 127 k, 1/16 W, 1% 1.5 M, 1/16 W, 1% 68.1 , 1/16 W, 1% 42.2 k, 1/16 W, 1% 1.8 M, 1/10 W, 1% 200 k, 1/16 W, 1% 301 , 1/16 W, 1% 1 M, 1/16 W, 1% 47 , 1/16 W, 5% 1.69 M, 1/16 W, 1% 8.2 , 1/16 W, 1% 150 , 1/16 W, 1% 2 , 1/16 W, 5% 6.2 M, 1/16 W, 1% 6.8 M, 1/16 W, 1% 10 , 1/16 W, 5%, or 220 H inductor 600 , 200 mA ferrite bead SIZB60, 600 V, 60 A bridge rectifier 350 V, 100 A Sidactor CPC5602 FET CPC5610 LITELINK
Suppliers
Panasonic, AVX, Novacap, Murata, SMEC, etc.
Panasonic, Electro Films, FMI, Vishay, etc.
Murata BLM11A601S or similar Shindengen, Diodes, Inc. Teccor, ST Microelectronics, TI Clare
components offer significant cost savings over SMT.
Rev. 9.0
www.clare.com
7
CPC5610/CPC5611 2.2 Reactive Termination Application Circuit
Figure 4. Reactive Termination Application Circuit Schematic
3.3 or 5 V R23 10 C16 10 FB1 600 200 mA A 1 R1 (RTX) 80.6K 1% TXTX+ C13 0.1 C2 0.1 C3 0.1 2 3 4 5 6 7 OH RING CID RXRX+ 8 9 VDD TXSM TXTX+ TX REFM GND OH RING
C1 1 C9 0.1 A U1 LITELINK REFL TXF ZTX ZNT TXSL BR1NTS GAT REFB DCS1 DCS2 ZDC BR2RPB RXS VDDL 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 R4 (RPB) 68.1 1% -BR R8 (RHTX) 200K 1% R9 (RHNT) 200K 1% R10 (RZNT1) 59 1% C20 (CZNT) 0.68 R11 (RZNT2) 169 1% -BR C7 (CSNP-) 220pF 2000V R3 (RSNPD) 1.5M 1% R6 (RSNP-2) 1.8M 1/10W 1% R44 (RSNP-1) 1.8M 1/10W 1% C11 (CZTX) 1.5 -BR NOTE: Unless otherwise noted, all resistors are in Ohms, 5%. All capacitors are in microFarads. R18 (RZTX1) 29.4 1% R19 (RZTX2) 84.5 1% SP1 P3100SB 1 TIP -BR R15 (RDCS2) 1.69M 1% R16 (RZDC) 22.1 1% R20 (RVDDL) 2 DB1 SIZB60 + 600V_60A R12 (RNTF) 287K 1% R14 (RGAT) 47 -BR C12 (CDCS) 0.027 R13 (RNTS) 1M 1% -BR R5 (RTXF) 42.2K 1% C10 0.01 500V C15 0.0022 500V
Q2 MMBT4126
-BR
Q1 CPC5602C
-BR
R22 (RDCS1A) 6.8 M 1% R21 (RDCS1B) 6.2 M 1%
10 CID C14 0.1 11 RXC4 0.1 12 RX+ 13 SNP+ 14 SNP15 RXF 16 RX R2 (RRXF) 127K 1%
C32 0.47 R74 10 1% -BR
-
A
-BR 2 RING
R7 (RSNP+2) C8 (CSNP+) 1.8M 1/10W 1% 220pF 2000V
1 This design was tested and found to comply with FCC Part 68 with this part. Other compliance requirements may require a different part. 2Higher-noise power supplies may require substitution of a 220 H inductor, Toko 380HB-2215 or similar. See the Power Quality section of Clare application note AN-146, Guidelines for Effective LITELINK Designs for more information.
R45 (RSNP+1) 1.8M 1/10W 1%
8
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Rev. 9.0
CPC5610/CPC5611
2.2.1 Reactive Termination Application Circuit Part List
Quantity 1 6 1 2 2 1 1 1 1 1 1 1 1 1 1 1 4 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
Reference Designator C1 C2, C3, C4, C9, C13, C14 C5 C7, C81 C101 C11 C12 C151 C16 C20 C32 R1 R2 R3 R4 R5 R6, R7, R44, R451 R8, R9 R10 R11 R12 R13 R14 R15 R16 R18 R19 R20 R21 R22 R23 R74 FB1 DB1 SP1 Q1 Q2 U1
Description 1 F, 16 V, 10% 0.1 F, 16 V, 10% 0.47 F, 16 V, 10% 220 pF, 2 kV, 5% 0.01 F, 500 V, 10% 1.5 F, 16 V, 10% 0.027 F, 16 V, 10% 0.0022 F, 500 V, 10% 10 F, 16 V, 10% 0.68 F, 16 V, 10% 0.47 F, 16 V, 10% 80.6 k, 1/16 W, 1% 127 k, 1/16 W, 1% 1.5 M, 1/16 W, 1% 68.1 , 1/16 W, 1% 42.2 k, 1/16 W, 1% 1.8 M, 1/10 W, 1% 200 k, 1/16 W, 1% 59 , 1/16 W, 1% 169 , 1/16 W, 1% 287 k, 1/16 W, 1% 1 M, 1/16 W, 1% 47 , 1/16 W, 5% 1.69 M, 1/16 W, 1% 22.1 , 1/16 W, 1% 29.4 , 1/16 W, 1% 84.5 , 1/16 W, 1% 2 , 1/16 W, 5% 6.2 M, 1/16 W, 1% 6.8 M, 1/16 W, 1% 10 , 1/16 W, 5%, or 220 H inductor 10 , 1/16 W, 1% 600 , 200 mA ferrite bead SIZB60, 600 V, 60 A bridge rectifier 350 V, 100 A Sidactor CPC5602 FET MMBT4126 CPC5610 LITELINK
Supplier
Panasonic, AVX, Novacap, Murata, SMEC, etc.
Panasonic, Electro Films, FMI, Vishay, etc.
Murata BLM11A601S or similar Shindengen, Diodes, Inc. Teccor, ST Microelectronics, TI Clare Fairchild Clare
Through-hole components offer significant cost savings over SMT.
Rev. 9.0
www.clare.com
9
CPC5610/CPC5611
3. Using LITELINK
As a full-featured telephone line interface, LITELINK performs the following functions: * * * * * * * * DC termination AC impedance control V/I slope control 2-wire to 4-wire conversion (hybrid) Current limiting Ring detection Caller ID signal reception Switch hook hook state, loop current flows through LITELINK and the system is answering or placing a call.
3.2 On-hook Operation
The LITELINK application circuit leakage current is less than 10 A with 100 V across ring and tip, equivalent to greater than 10 M on-hook resistance.
LITELINK can accommodate specific application features without sacrificing basic functionality and performance. Application features include, but are not limited to: * * * * * * * * High gain (+3 dBm) operation Pulse dialing Ground start Loop start Parallel telephone off-hook detection (911 feature) Battery reversal Line presence World-wide programmable operation
3.2.1 Ring Signal Detection via the Snoop Circuit
In the on-hook state (OH and CID not asserted), an internal multiplexer turns on the snoop circuit. This circuit monitors the telephone line for two conditions; an incoming ring signal, and caller ID data bursts. Refer to the application schematic diagram (see Figure 3 on page 6). C7 (CSNP-) and C8 (CSNP+) provide a high-voltage isolation barrier between the telephone line and SNP- and SNP+ on the LITELINK while coupling AC signals to the snoop amplifier. The snoop circuit "snoops" the telephone line continuously while drawing no current. In the LITELINK, ringing signals are compared to a threshold. The comparator output forms the RING signal output from LITELINK. This signal must be qualified by the host system as a valid ringing signal. A low level on RING indicates that the LITELINK ring signal threshold has been exceeded. For the CPC5610 (with the half-wave ring detector), the frequency of the RING output follows the frequency of the ringing signal from the central office (CO), typically 20 Hz. The RING output of the CPC5611 (with the full-wave ring detector) is twice the ringing signal frequency. Hysteresis is employed in the LITELINK ring detector circuit to provide noise immunity. The setup of the ring detector comparator causes RING output pulses to remain low for most of the ringing signal half-cycle. The RING output returns high for the entire negative half-cycle of the ringing signal for the CPC5610. For the CPC5611, the RING output returns high for a short period near the zero-crossing of the ringing signal before returning low during the positive half-cycle. For both the CPC5610 and CPC5611, the RING output remains high between ringing signal bursts. The ring detection threshold depends on the values of R3 (RSNPD), R6 (RSNP-), R7 (RSNP+), C7 (CSNP-), and C8 (CSNP+). The values for these components shown in the typical application circuits are recommended for
This section of the data sheet describes LITELINK operation in standard configuration for usual operation. Clare offers additional application information online (see Section 5 on page 14). These include information on the following topics: * * * * * * Circuit isolation considerations Optimizing LITELINK performance Data Access Arrangement architecture LITELINK circuit descriptions Surge protection EMI considerations
Other specific application materials are also referenced in this section as appropriate.
3.1 Switch Hook Control (On-hook and Off-hook States)
LITELINK operates in one of two conditions, on-hook and off-hook. In the on-hook condition the telephone line is available for calls. In the off-hook condition the telephone line is engaged. Use the OH control input to place LITELINK in one of these two states. With OH high, LITELINK is on-hook and ready to make or receive a call. The snoop circuit is enabled. Assert OH low to place LITELINK in the off-hook state. In the off10
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CPC5610/CPC5611
typical operation. The ring detection threshold can be changed according to the following formula:
750mV V RINGPK = ---------------- R3
2 1 ( 2R 6 + R 3 ) + ------------------------------2 ( f RING C 7 )
In North American applications, follow these steps to receive on-hook caller ID data via the LITELINK RX outputs: 1. 2. 3. 4. Detect the first ringing signal outputs on RING. Assert CID low. Process the CID data from the RX outputs. De-assert CID (high or floating).
Clare Application Note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold is a spreadsheet for trying different component values in this circuit. Changing the ring detection threshold will also change the caller ID gain and the timing of the polarity reversal detection pulse, if used.
Note: Taking LITELINK off-hook (via the OH pin) disconnects the snoop path from both the receive outputs and the RING output, regardless of the state of the CID pin. CID gain from tip and ring to RX+ and RX- is determined by:
3.2.2 Polarity Reversal Detection with CPC5611
The full-wave ring detector in the CPC5611 makes it possible to detect tip and ring polarity reversal using the RING output. When the polarity of tip and ring reverses, a pulse on RING indicates the event. Your host system must be able to discriminate this single pulse of approximately 1 msec (using the recommended snoop circuit external components) from a valid ringing signal.
6R 3 GAIN CID ( dB ) = 20 log ---------------------------------------------------------------2 1 ( 2R 6 + R 3 ) + -----------------2 ( fC 7 )
where is the frequency of the CID data signal. The recommended components in the application circuit yield a gain 0.27 dB at 200 Hz. Clare Application Note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold is a spreadsheet for trying different component values in this circuit. Changing the CID gain will also change the ring detection threshold and the timing of the polarity reversal detection pulse, if used. For single-ended snoop circuit output of 0 dBm, set the total resistance across the series resistors (R6/ R44 and R7/R45) to 1.4 M.
3.2.3 On-hook Caller ID Signal Processing
On-hook caller ID (CID) signals are processed by LITELINK by coupling the CID data burst through the snoop circuit to the LITELINK RX outputs under control of the CID pin. In North America, CID data signals are typically sent between the first and second ringing signal.
Figure 5. On-hook Caller ID Signal Timing in North America for CPC5610 (with Halfwave Ring Detect)
2s 500 ms 3s 475 ms 2s
3.3 Off-Hook Operation
Caller ID data
3.3.1 Receive Signal Path
Signals to and from the telephone network appear on the tip and ring connections of the application circuit. Receive signals are extracted from transmit signals by the LITELINK two-wire to four-wire hybrid. Next, the receive signal is converted to infrared light by the receive photodiode amplifier and receive path LED. The intensity of the light is modulated by the receive signal and coupled across the electrical isolation barrier by a reflective dome. On the host equipment side of the barrier, the receive signal is converted by a photodiode into a photocurwww.clare.com 11
RING First Ring
Second Ring
CID
Signal levels not to scale
Rev. 9.0
CPC5610/CPC5611
rent. The photocurrent, a linear representation of the receive signal, is amplified and converted to a differential voltage output on RX+ and RX-. Variations in gain are controlled to within 1 dB by an on-chip automatic gain control (AGC) circuit, which sets the output of the photoamplifier to unity gain. To accommodate single-supply operation, LITELINK includes a small DC bias on the RX outputs of 1.0 Vdc. Most applications should AC couple the RX outputs as shown in Figure 6. LITELINK may be used for differential or single-ended output as shown in Figure 6. Single-ended use will produce 6 dB less signal output amplitude. Do not exceed 0 dBm into 600 (2.2 VP-P) signal input. Figure 7. Differential and Single-ended Transmit Path Connections to LITELINK
Host CODEC or Transmit Circuit LITELINK
0.1uf TXA1 TXA2 0.1uf
TXTX+
+
Host CODEC or Transmit Circuit
LITELINK
0.1uf TXA1 0.1uf
TXTX+
+
Figure 6. Differential and Single-ended Receive Path Connections to LITELINK
Host-side CODEC or Voice Circuit
RX+ RX0.1uF 0.1uF RX-
LITELINK
3.4 DC Characteristics
The CPC5610 and CPC5611 are designed for worldwide application regarding DC characteristics, including use under the requirements of TBR-21. The ZDC, DCS1, and DCS2 pins control the VI slope characteristics of LITELINK. Selecting appropriate resistor values for RZDC (R16) and RDCS (R15) in the provided application circuits assure compliance with DC requirements.
RX+
RX
0.1uF
RX+
3.4.1 Resistive Termination Applications
LITELINK includes a telephone line current limit feature that is selectable by selecting the desired value for RZDC (R16) using the following formula:
3.3.2 Transmit Signal Path
Connect transmit signals from the host equipment to the TX+ and TX- pins of LITELINK. Do not exceed a signal level of 0 dBm in 600 (or 2.2 VP-P). Differential transmit signals are converted to single-ended signals in LITELINK. The signal is coupled to the transmit photodiode amplifier in a similar manner to the receive path. The output of the photodiode amplifier is coupled to a voltage-to-current converter via a transconductance stage where the transmit signal modulates the telephone line loop current. As in the receive path, gain is set to unity automatically, limiting insertion loss to 0, 1 dB.
1V I CL Amps = ------------ + 0.011A R ZDC
Clare recommends using 8.2 for RZDC in North America and Japan, limiting telephone line current to 133 mA.
3.4.2 Reactive Termination Applications
TBR-21 sets the telephone line current limit at 60 mA. To meet this requirement, set RZDC (R16) to 22.1 . See Clare application note AN-146 Guidelines for Effective LITELINK Designs for information on FET heat sinking in this application.
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CPC5610/CPC5611 3.5 AC Characteristics
3.5.1 Resistive Termination Applications
North American and Japanese telephone line AC termination requirements are met with a resistive 600 AC termination. Receive termination is applied to the LITELINK ZNT pin (pin 29) as a 301 resistor, RZNT (R10). A 150 resistor, R18 (RZTX), applied to the LITELINK ZTX pin (pin 30) sets the correct transmit gain and impedance. The information provided in this document is intended to inform the equipment designer but it is not sufficient to assure proper system design or regulatory compliance. Since it is the equipment manufacturer's responsibility to have their equipment properly designed to conform to all relevant regulations, designers using LITELINK are advised to carefully verify that their endproduct design complies with all applicable safety, EMC, and other relevant standards and regulations. Semiconductor components are not rated to withstand electrical overstress or electro-static discharges resulting from inadequate protection measures at the board or system level.
3.5.2 Reactive Termination Applications
Many areas use a single-pole complex impedance to model the telephone network transmission line characteristic impedance as shown in the table below. Line Impedance Model TBR-21 Ra Rb C 750 270 150 nF 820 220 120 nF Australian
Matching a complex impedance requires the use of complex networks on ZNT and ZTX. In order to accommodate high power levels, it is necessary to modify the transmit and receive gain characteristics of your LITELINK implementation. The complex network on the ZTX pin increases transmit gain by 7 dB. A 7 dB pad may be inserted before the TX+ and TX- pins to provide overall unity gain. Similarly, with a complex network, the ratio of R12 (RNTF) and R13 (RNTS) must be modified from 1:1 to 1:.287, which introduces a 7 dB loss in the receive path from tip and ring to ZNT.
4. Regulatory Information
LITELINK can be used to build products that comply with the requirements of TIA/EIA/IS-968 (formerly FCC part 68), FCC part 15B, TBR-21, EN60950, UL1950, EN55022B, IEC950/IEC60950, CISPR22B, EN55024, and many other standards. LITELINK complies with the requirements of UL1577. LITELINK provides supplementary isolation. Metallic surge requirements are met through the inclusion of a Sidactor in the application circuit. Longitudinal surge protection is provided by LITELINK's optical-across-thebarrier technology and the use of high-voltage components in the application circuit as needed.
Rev. 9.0
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CPC5610/CPC5611
5. LITELINK Design Resources
5.1 Clare, Inc. Design Resources
The Clare, Inc. web site has a wealth of information useful for designing with LITELINK, including application notes and reference designs that already meet all applicable regulatory requirements. LITELINK data sheets also contains additional application and design information. See the following links: LITELINK datasheets and reference designs Application note AN-107 LOCxx Series - Isolated Amplifier Design Principles Application note AN-114 ITC117P Application note AN-117 Customize Caller-ID Gain and Ring Detect Voltage Threshold for CPC5610/11 Application note AN-140, Understanding LITELINK Application note AN-141, Enhanced Pulse Dialing with LITELINK Application note AN-143, Loop Reversal Detection with LITELINK Application note AN-146, Guidelines for Effective LITELINK Designs Application note AN-147, Worldwide Application of LITELINK Application note AN-149, Increased LITELINK II Transmit Power Application note AN-150, Ground-start Supervision Circuit Using IAA110 Photodiode Amplifiers: Op Amp Solutions, Jerald Graeme, McGraw-Hill Professional Publishing; ISBN: 007024247X Teccor, Inc. Surge Protection Products United States Code of Federal Regulations, CFR 47 Part 68.3
5.2 Third Party Design Resources
The following also contain information useful for DAA designs. All of the books are available on amazon.com. Understanding Telephone Electronics, Stephen J. Bigelow, et. al., Butterworth-Heinemann; ISBN: 0750671750 Newton's Telecom Dictionary, Harry Newton, CMP Books; ISBN: 1578200695 14 www.clare.com
Rev. 9.0
CPC5610/CPC5611
6. LITELINK Performance
The following graphs show LITELINK performance using the North American application circuit shown in this data sheet.
Figure 8. Receive Frequency Response at RX
+3 +2.5 +2 +1.5 +1 +0.5 -0 Gain (dBm) -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5 20 50 100 200 Frequency (Hz) 500 1K 2K 4K
Figure 10. Receive THD on RX
dB
Frequency (Hz)
Figure 9. Transmit Frequency Response at TX
+3 +2.5 +2 +1.5 +1 +0.5 -0 Gain (dBm) -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5 20 50 100 200 Frequency (Hz)
Frequency (Hz) dB
Figure 11. Transmit THD on Tip and Ring
500
1K
2K
4K
Rev. 9.0
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CPC5610/CPC5611
Figure 12. Trans-Hybrid Loss
-15
Figure 14. Snoop Circuit Frequency Response
5
-20
0
-25
-5
THL -30 (dB)
Gain (dBm ) -10
-35
-40
-15
-45 300 800 1300 1800 2300 2800 3300 Frequency (Hz) Without C18 With C18
-20
-25 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency (Hz)
Figure 13. Return Loss
60
Figure 15. Snoop Circuit THD + N
55
50
Return Loss 45 (dB)
40
35
30 0 500 1000 1500 2000 Frequency (Hz) 2500 3000 3500 4000
500 1K 1.5K 2K 2.5K 3K 3.5K 4K
Hz
Figure 16. Snoop Circuit Common Mode Rejection
+0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5 -20 -22.5 -25 -27.5 CMRR -30 (dBm) -32.5 -35 -37.5 -40 -42.5 -45 -47.5 -50 -52.5 -55 -57.5 -60 20 50 100 200 Frequency (Hz) 500 1K 2K 4K
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CPC5610/CPC5611
7. Manufacturing Information
7.1 Mechanical Dimensions
Figure 17. Dimensions
10.287 + .254 (0.405 + 0.010) 4 Max. 32 PL
7.493 + 0.127 (0.295 + 0.005)
10.363 + 0.127 (0.408 + 0.005) 0.635 x 45 (0.025 x 45)
7.239 + 0.051 (0.285 + 0.002)
1.016 Typ. (0.040 Typ.) 0.203 (0.008)
0.635 + 0.076 (0.025 + 0.003)
2.134 Max. (0.084 Max.)
1.981 + 0.051 (0.078 + 0.002) A 0.330 + 0.051 (0.013 + 0.002) 9.525 + 0.076 (0.375 + 0.003) 0.051 + 0.051 (0.002 + 0.002)
DIMENSIONS
mm (Inches)
Coplanar to A 0.08/(0.003) 32 PL.
Figure 18. Recommended Printed Circuit Board Layout
11.380 (0.448) 1.650 (0.065)
0.635 (0.025)
0.330 (0.013)
9.730 (0.383)
Rev. 9.0
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7.2 Tape and Reel Packaging
Figure 19. Tape and Reel Dimensions
330.2 DIA. (13.00) Top Cover Tape Thickness .102 MAX. (.004) 12.090 (.476) 6.731 MAX. (.265) 1.753 .102 (.069 .004) .406 MAX. (.016) 7.493 .102 (.295 .004) 3.20 (.126) 2.70 (.106) 2.007 .102 1.498 .102 3.987 .102 (.079 .004)(.059 .004) (.157 .004)
16.002 .305 (.630 .012) 10.693 .025 (.421 .001)
Embossed Carrier
Top Cover Tape Embossment
.050R TYP.
11.989 .102 (.472 .004) Feed Direction
10.897 .025 (.429 .001)
1.549 .102 (.061 .004)
Dimensions mm (inches)
7.3 Soldering
7.3.1 Moisture Reflow Sensitivity
Clare has characterized the moisture reflow sensitivity of LITELINK using IPC/JEDEC standard J-STD-020A. Moisture uptake from atmospheric humidity occurs by diffusion. During the solder reflow process, in which the component is attached to the PCB, the whole body of the component is exposed to high process temperatures. The combination of moisture uptake and high reflow soldering temperatures may lead to moisture induced delamination and cracking of the component. To prevent this, this component must be handled in accordance with IPC/JEDEC standard J-STD-020A per the labeled moisture sensitivity level (MSL), level 3.
which were used to determine the moisture sensitivity level of this component.
7.4 Washing
Clare does not recommend ultrasonic cleaning of this part.
7.3.2 Reflow Profile
The maximum ramp rates, dwell times, and temperatures of the assembly reflow profile should not exceed those specified in IPC/JEDEC standard J-STD-020A, For additional information please visit www.clare.com
Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC5610/CPC5611-R9.0 Copyright (c) 2002, Clare, Inc. All rights reserved. Printed in USA. 6/27/2002

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